发明名称 |
FORMATION OF MULTILAYER INTERCONNECTION |
摘要 |
PURPOSE:To reduce disconnection of wiring by eliminating a difference in level produced when the second layer wiring is formed on the first layer wiring so as to make the substrate flat. CONSTITUTION:The first layer wiring 2 is formed on a semiconductor substrate 1 and an insulating film 3 of almost the same thickness as the wiring 2 is deposited on the whole surface. In a recess of the film 3, a resist pattern 4 is formed in a manner a thickness of it becomes the same as a projecting part of the film 3. The resist of the same quality is spread over the whole surface and the surface of a resist film 7 is levelled. Then the film 7 and the film 3 are etched at the same velocity. Consequently, the projecting part of the film 3 is eliminated and the substrate can be levelled regardless of a size of the level difference due to a base wiring. Subsequently, an interlaminar insulating film 8 is formed and contact holes 6 are opened in the predetermined positions thereby forming the second layer wiring 5 on the film 8. By such constitution, there is no possibility of disconnection of wiring and it becomes possible to improvement in reliability and integration. |
申请公布号 |
JPS61116861(A) |
申请公布日期 |
1986.06.04 |
申请号 |
JP19840238136 |
申请日期 |
1984.11.12 |
申请人 |
SUMITOMO ELECTRIC IND LTD |
发明人 |
FUKUDA KEIICHI;EHATA TOSHIKI |
分类号 |
H01L21/3205;(IPC1-7):H01L21/88 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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