| 摘要 |
<p>PURPOSE:To latch the 2nd latch circuit by equipping a memory circuit and the 2nd latch circuit between a latch circuit between a latch circuit and a parallel/serial shift register and code-converting a code character of four bits into the code system of a decode circuit at the reception side. CONSTITUTION:Receiving an encoded reception data S20 and a quick clock S21, a changing point detection circuit C11 outputs signal lines S23 and S24 for showing at which phase the data S20 is encoded and the polarity S25 of the data. Receiving a clock S22, a clock generator circuit C12 outputs clocks S26-S29 having phases shifted by 90 deg. each. By the signal lines S23 and S24 a selection circuit C13 selects and outputs any one of four clocks S26-S29 to a signal line S30. Thus the code character of the changing point encoding system at the transmission side can be stored in a memory circuit without modifying the circuit constitution of the encoding circuit, and a code is converted in the memory circuit, whereby the code character can be converted into the one matching to the decoder circuit at the reception side to be transmitted.</p> |
