| 摘要 |
A plurality of computer stations each includes a data processing computer capable of having its data processing function inhibited or halted by a halt signal applied to a halt input terminal, and each also includes a random access memory (RAM). The plurality of computer stations are interconnected by a bus system and controlled by a bus controller for allowing the periodic interchange of data among the random access memories of the computer stations. The bus controller periodically generates a halt signal which is applied in common to the halt input terminal of each computer station and which stops the processing of data by each data processing computer during the interchange of data. During the time of each halt signal, the bus controller generates in time sequence computer station address signals which are applied in common over the bus system to an address decoder associated with each computer station. The decoder associated with the particular computer station being addressed produce a second output signal, and all the other decoders produce a second output signal. Thus, the bus controller periodically accesses each computer station. During the time in which each computer station is accessed, the bus controller produces in predetermined time sequence one or more word addresses, each representing the memory location of a word to be read from the RAM of the computer station which is addressed and also representing the memory location into which the word is to be written into the RAMs of those computer stations which are not addressed. The bus controller also generates read/write signals in conjunction with each word address. A first gating circuit associated with each computer station responds to the simultaneous occurrence of the halt and read/write signals and the first output signal of the decoder to generate a read signal for causing the RAM associated with the addressed computer station to read, and also responsive to the second output signal from the decoder to cause the RAM to write when the computer station is not addressed. A second gating circuit is coupled to each decoder, to each RAM and to the bus and is responsive to the first output signal from the decoder to couple the word read therefrom to a particular portion of the bus system, and is responsive to the second output signal from the decoder to couple signal from the particular portion of the bus to the RAM for writing in.
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