SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PATTERN LAYOUT THEREFOR

摘要

PURPOSE:To provide via contact holes with less positional errors by a method wherein the center line of a via contact hole is made to be in line with the center line of a wiring layer formed on a substrate. CONSTITUTION:An Al wiring 36a runs over a cell row 312 and its end is connected to an end of an Al wiring 34c in a wiring region 332 through a via contact hole 38. Under the via contact hole 38, a wiring layer 35b is located. A pattern is laid out wherein the center line of the wiring layer 35b coincides with the center line of the via contact hole 38.