发明名称 DETECTION CIRCUIT OF MALFUNCTION OF SCAN BUS
摘要 PURPOSE:To make a shift action have a high reliability by providing a gate circuit for outputting the output of a comparator circuit only when a scan bus is shifted with the output of the comparator circuit and a signal for showing that the data bus is being shifted as an input. CONSTITUTION:The 1st circuit 5 and the 2nd circuit 7 output an exclusive OR of flip-flops 1-3 and that of flip-flops 2-4 to signal lines 106 and 108, respectively. A flip-flop 6 outputs the output 106 of the 1st circuit 5 to a signal line 107 after it delays the output 106 by one clock cycle with the aid of a clock 105. The comparator circuit 8 compares signal lines 107 and 108, and outputs a logic '0' and a logic '1' to a signal line 109 when both logics are equal and when they are unequal, respectively. When logics of the signal lines 106 and 108, that is, the outputs of the 1st and 2nd circuits 5 and 7 for outputting exclusive ORs invert, it means that the malfunction occurred during a shift action. Thus such a circuit is incorporated in the scan bus of a data processor; therefore malfunction during the shift action of the scan bus can be detected.
申请公布号 JPS61115143(A) 申请公布日期 1986.06.02
申请号 JP19840236397 申请日期 1984.11.09
申请人 NEC CORP 发明人 HATTORI TOSHIYUKI
分类号 G06F11/22;G06F11/267;H01L21/822;H01L27/04 主分类号 G06F11/22
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