发明名称 POWER FAILURE DETECTING METHOD
摘要 PURPOSE:To secure the data obtained before a power failure occurs by initializing the actuation of a processing means when the outputs of both the 1st and 2nd detecting means for power supply voltage of a switching means set between a power supply and the processing means are set at an equal level and keeping an active state of the processing means when said both outputs are set at different levels. CONSTITUTION:An end of an AC power supply E is connected to an input terminal at one side of a DC power supply 4 via a line l1, a power supply switch 3 and a line l2. While the other end of the source E is connected to the other input terminal of the source 4 via a line l3. The input terminals of voltage detecting circuits 1 and 2 are connected to lines l1 and l3 and lines l2 and l3 respectively, and the source 4 is connected to a controller 5 connected to an input device 6 and an output device 7. Furthermore the output terminals of the circuit 1 are connected to the input terminals at one side of gate circuits 8 and 9 respectively. While the output terminals of the circuit 2 are connected to the input terminals at the other side of the circuits 8 and 9 respectively. The outputs of both circuits 8 and 9 are applied to the set and reset terminals of an FF10. Thus the signal of a high level of the FF10 is supplied to the controller 5 in a power failure mode to secure the state set before the power failure occurs.
申请公布号 JPS61114321(A) 申请公布日期 1986.06.02
申请号 JP19840234316 申请日期 1984.11.07
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 NAMIKOSHI YASUMASA
分类号 H02J1/00;G06F1/00;G06F1/28;G06F1/30;H02H3/24 主分类号 H02J1/00
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