| 摘要 |
PURPOSE:To prevent the overrun of data from the transmission side due to the delay or stoppage of processing at the reception side by inhibiting data transfer to a communications line where an overrun counter decreased whenever it receives information from an informing means exceeds a plural number (n). CONSTITUTION:When buffer registers 13 of n-stages connected to a data processing part 4 are idle, a buffer register set timing circuit 20 sets sequentially the registers so that the initial contents of the buffer registers 13 can be shifted. Accordingly a timing generator circuit 16 in a data transmitter 101 will not transmit data at a higher speed than the shift action of the buffer register 13. When a zero detector 22 detects zero of the 1st counter 6, a data transfer control part 8 stops a set standby signal 11 to terminate the data transfer. Until a counter 5 at the side of a data processor 100 goes to zero, a data processing signal 23 is transmitted to a data transmitter 101 to subtract the 2nd counter 9. Thus data can be transferred at a high speed by matching to the data processing ability of the data processor 100.
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