发明名称 HOLDING CIRCUIT
摘要 PURPOSE:To quicken the signal transmission speed from an input terminal to an output terminal by adding an MOSFET conductive at all times and having a long channel length to a holding circuit comprising two MOSFETs. CONSTITUTION:A potential of the 2nd potential point 4 is impressed to a gate of an FET 8, which is made always conductive. Further, a potential of the 1st potential point 3 is impressed to a gate of an FET 9, which is made normally conductive. When an H level input signal is inputted to the input terminal 1 and the FET 5 is made conductive, the trhough-current is suppressed by the FET 8 having a long channel length. Similarly, the through-current at the conduction of the FET 6 is suppressed by the FET 9 having a long channel length. Thus, the channel length of the FETs 5,6 is reduced to decrease the gate capacitance. Then the load of an inverter 7 is decreased and the signal transmission speed from the input terminal to the output terminal is increased.
申请公布号 JPS61113319(A) 申请公布日期 1986.05.31
申请号 JP19840236424 申请日期 1984.11.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 HASEGAWA KENJI
分类号 H03K17/687;H03K3/356 主分类号 H03K17/687
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