| 摘要 |
PURPOSE:To reduce substantially the test time by latching simultaneously a row address signal and a bank selecting signal when a row address strobe signal is activated and driving selectively plural memory cell arrays activated selectively on the basis of information. CONSTITUTION:The titled memory has separately the bank selecting signal BSi as an address input for selecting a bank in addition to the address input of a conventional multiaddress-type DRAM. Due to the rise of the row address strobe signal RAS the memory cell is activated to latch and fetch a row address into the interior. Simultaneously the bank selecting address is latched. Based on the latch information a column address strobe signal system circuit 801, that is, the multiaddress-type DRAM, selectively activates circuit systems for operating followed by column decoders 501-505 among plural column address buffers, a decoder, an I/O data amplifier and an I/O data control system. For instance, only a column selecting inner signal CASi is activated, and the read action of the selective memory cell array is completed.
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