| 摘要 |
PURPOSE:To reduce input wiring resistance and to improve display irregularity, delay of data timing, etc., by arranging the same input terminals of LSI chips and connecting the same input terminals of the adjacent LSI chips to each other. CONSTITUTION:The LSI chips 11 and 12 have the same input terminals B1 and B2, and C1 and C2 symmetrically about center input terminals A. External terminals 13 and LSI chips 11 and 12 formed on a lower substrate 10 are connected through wiring parts 14 and 15 formed on multilayered metallic films on the lower electrode substrate 10. The wiring 14 connects an external terminal 13A and A of the LSI chips 11, an external terminal 13B and B1 of the LSI chip 11, and an external terminal 13C and C1 of the LSI chip 11, i.e. the same input terminals mutually. The wiring 15 also connects A of the LSI chip 11 and A of the LSI chip 12, B2 of the LSI chip 11 and B1 of the LSI chip 12, and C2 of the LSI chip 11 and C1 of the LSI chip 12, i.e. the same input terminals mutually.
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