| 摘要 |
PURPOSE:To reduce a scattered type frame synchronization restoration time by delaying a frame synchronizing signal arranged scattering in equal interval for a prescribed time, comparing it with a local frame synchronizing signal and processing the result. CONSTITUTION:When a digital signal having a scattered frame synchronizing signal arranged scatteredly in one frame at an equal interval is inputted to a distribution circuit 10, the signal is distributed into sub frames with an equal interval in the order of inputs. Each distributed sub frame is delayed for a prescribed time by delay circuits 201-20k-1 and the scattered frame synchronizing signal in one frame are outputted in parallel in the same timing. A detection circuit 30 compares the output of the circuits 201-20k-1 and the circuit 10 with the local frame synchronizing signal inputted in parallel from a local frame counter 40, and when the coincidence is detected, a frame synchronizing signal detection signal is outputted to a protection circuit 50. When the circuit 50 confirms that the synchronization is executed for a pescribed number of times, a level 1 is outputted to an OR gate 60, the counter 40 counts the clock via the gate 60, a delay circuit 80 and an AND gate 70 to take timing generation of the local frame synchronizing signal. |
