发明名称 MOS FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF
摘要 PURPOSE:To suppress the yield of hot carriers and to avoid a capturing phenomenon of the carriers at an interface between an impurity region with relatively low concentration and a side wall insulating film, by forming source and drain regions by three-layer structure comprising the relatively low-concentration impurity region, an impurity regions having higher concentration and an impurity regions having more higher concentration. CONSTITUTION:Source and drain regions 4 a have a three-layer structure of an N<-> region, 4C, an N<+> region 4D and an N<++> region 4E. The N<->, N<+> and N<++> regions have the impurity concentrations in the order of - 10<12>, - 10<-13>, and - 10<14> pieces/cm<2>, respectively. The N<-> region 4C is embedded beneath a gate electrode 3. The N<+> region 4D and the N<++> region 4E are located beneath a side wall SiO2 film 5. In this constitution, the hot carrier suppressing effect provided in an LDD structure is maintained by the presence of the N<-> region 4C. In the meantime, the disadvantage of carrier capturing in the LDD structure at the interface between the relatively low-concentration impurity region constituting the source and drain and the side wall insulating film can be avoided.
申请公布号 JPS61112379(A) 申请公布日期 1986.05.30
申请号 JP19840233101 申请日期 1984.11.07
申请人 HITACHI LTD 发明人 AZUMA TAKASHI
分类号 H01L21/265;H01L29/78 主分类号 H01L21/265
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