| 摘要 |
PURPOSE:To improve the working speed of a peripheral speed as well as the degree of designing freedom by providing a means to each peripheral circuit to produce a request signal that delays an access to a CPU until the preparation is through with transfer of data. CONSTITUTION:A decoder 12 which decodes the address signal delivered onto a bus 7 from a CPU 1 and selects the corresponding register 11 is provided within a peripheral circuit like a timer circuit 5 together with an AND gate 13 which secures an AND between the timing signal tC delivered from a control part 9 that controls the circuit 5 and the output of the decoder 12, and a flip- flop 14 which is set and reset by the output of the gate 13. The output Q of the flip-flop 14 is supplied to the CPU 1 as a wait signal. Therefore an access state is delayed until the cycle in the circuit 5 proceeds to the tC although the CPU 1 proceeds to the read/write cycle of the register 11. |
