| 摘要 |
PURPOSE:To facilitate reduction of an additional area used for check even no in case the number N of memory cells to be checked can hardly be executed the square root to a natural number, by dividing a memory cell array into many parts and switching these parts by a column switch to carry out the horizontal/vertical parity check. CONSTITUTION:A memory cell array 1 is substantially divided into two parts by providing 1024 pieces of column switches 11 and 12 between the array 1 and a selector circuit 3. In the same way, 32 pieces of column switches 13 and 14 are set between a parity check cell array 2 and the circuit 3. Thus these arrays are divided and sent to the circuit 3. Here the switches 11 and 13 are coupled together for actuation together with switches 12 and 14 coupled together respectively. Thus the array 1 can be divided even in case the number N of memory cells can have no extraction of the root to a natural number. This attains reduction of an additional area for horizontal/vertical parity check.
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