发明名称 BUFFER CONTROL SYSTEM
摘要 PURPOSE:To invalidate the copies of main memories in the buffers of plural processors connected to buses by flowing the replaced address information through the buses when the contents of the main memory are replaced. CONSTITUTION:Processors 1-4 containing buffers 11-14 which hold the copies of information on a main memory 9 are connected to buses 7 and 8 connected to the memory 9 via a memory access controller 5. When one of those processors writes the information to the memory 9, the controller 5 sends an access end command onto the bus 8. Each processor detects said end command and compares the address information with the copy address contained in the buffer. Then said copy is invalidated when the coincidence of comparison is obtained.
申请公布号 JPS61112258(A) 申请公布日期 1986.05.30
申请号 JP19840216588 申请日期 1984.10.16
申请人 FUJITSU LTD 发明人 NINOI EIZOU
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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