发明名称 GENERATING CIRCUIT OF CHIP SELECTION SIGNAL
摘要 PURPOSE:To attain an easy and free change of the address mapping of peripheral elements by decoding the address signal sent from a CPU through an RAM and producing a chip selection signal. CONSTITUTION:When a CPU1 writes the decoding data to a decoding RAM 8, the signal is delivered to a starting ROM 11 from a decoder circuit 9. Then data are written to the RAM 8 by a program stored in the ROM 11. When the address signal given from the CPU 1 exceeds a certain numerical value, a bidirectional multiplexer 10 connects the data input/output terminal of the RAM 8 to chip selection signal lines 6-1-6-n. Then the read signal and the RAM chip selection signal are sent to the RAM 8 from the circuit 9. Thus the chip selection signal is produced and one of peripheral elements 3-1-3-n is selected.
申请公布号 JPS61112265(A) 申请公布日期 1986.05.30
申请号 JP19840234772 申请日期 1984.11.05
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANAHASHI JUNICHI
分类号 G06F13/14 主分类号 G06F13/14
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