| 摘要 |
PURPOSE:To attain the conversion of a short pulse width by connecting a transistor (TR) between input terminals of inverters of the prestage and the pose-stage in a pulse width converting circuit comprising two-stages of inverters having a resistor and a load capacitor at the midpoint. CONSTITUTION:When input terminals 6,9 reach a high level, FETs6,9 are turned on to bring the level of nodes 41,42 to a low level. When the node 42 reaches the low level, since it is discharged directly by the FET9, the signal fall time is decreased. When the node 42 goest to the high level, it is charged up via a resistor R2 and the FET9 does not give any effect on the rise time. Since the minimum pulse width possible for conversion depends on the signal fall time, it is possible to convert the short pulse width. |
