| 摘要 |
<p>PURPOSE:To allow a drive circuit to control substantially a white level part of recording paper by generating a clock signal from a host CPU and generating newly a write effective signal from the host CPU or an image reader and giving both the signals to the drive circuit so as to attain accurate optical write to a photosensitive body. CONSTITUTION:A recording data 16a is inputted from the host CPU via an interface section 24 in a timing control section 25 of a recording control section 4 and outputted to an AND gate 31 from an FF28 synchronously with the trailing of a clock signal 30 inputted from the host CPU. When a write effective signal 36 is inputted to an FF34 from the host CPU, a recording data 16c is outputted to a shift register 18 from a gate 31. On the other hand, the clock signal 30 exceeding a preset value 40 is inputted to a counter 39 before the write effective signal 36 is inputted, the recording data 16c is blocked from being outputted to the shift register 18 in the route of FF35, NAND gate 38 and AND gate 31.</p> |
