发明名称 LARGE SCALE INTEGRATED CIRCUIT TEST SYSTEM
摘要 PURPOSE:To execute easily test a by using a test mode indicating terminal for the test of a built-in read/write storage circuit and changing a terminal to be used only for outputs to a two-way terminal. CONSTITUTION:When a test mode indicating signal 102 is turned to '1', a test mode indication NOT signal 103 is turned to ''0''. When a test mode is excited, buffers 9, 11 are activated, two-way signals 110, 111 are inputted and two-way input buffer signals 112, 113 are supplied to a data selecting circuit 3 and an address supplying circuit 5 respectively as the data and address of the read/write storage circuit 6 and output signals 105, 107 are supplied from the circuits 3, 5 to the circuit 6 as the data and address. When a writing signal 101 is activated, the data are written and stored in the circuit 6. A shift signal 115 for shifting only a reading register circuit 13 is added at the reading of data in case of the test mode to shorten reading. Since the signal 102 and the shift signal 115 are added and the terminal to be used as an output terminal is switched to a two-way terminal, the circuit 6 can be easily tested and the data can be read out rapidly.
申请公布号 JPS61111472(A) 申请公布日期 1986.05.29
申请号 JP19840233830 申请日期 1984.11.06
申请人 NEC ENG LTD 发明人 KAWADA KAZUHIRO
分类号 G01R31/28;G03B5/00;G03B17/00 主分类号 G01R31/28
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