| 摘要 |
A bus arrangement circuit for a multi-processing system in robots uses a memory bank in common with multi-processors having different bit units (8 bit and 16 bit system). The data is sequentially stored or drawn by an interface circuit. The 16 bit CPU(1b) is connected to the common RAM(#1a) through the buffer(BUF1) and demultiplexer(DEMUX) and the 8 bit CPUs (#2a,#3a) are connected to the multiplexer bus(MUX-BUS). An interface circuit(11) comprised of flip-flop circuits(FF1-2), inverters(D1-3, NAND gates (N1-5), AND gate(A1), and buffers(BUF2-3) controls the mutual data communication between different processors.
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