| 摘要 |
<p>PURPOSE:To read a correct count without increasing the load of the software processing by holding the input of a count clock so as to hold the count during a period from the read of a counter among n-set of series connection counters until at least (n) times of read. CONSTITUTION:Counters 11, 12 are of 8-bit constitution. When the content of the series connection counters in reading the counter 11 is 3FFFH, OFFH is read, and a holding circuit 3 continues to output the state of a count clock 4 to the counter 11 as a clock 4' at the input of a signal 5 by using a count holding signal 5 outputted from a holding circuit 3 at the execution of a read instruction of the counter 11 until a count holding release signals 6 is outputted by the execution of a read instruction of the counter 12 further. Even if the count clock rises after the counter 11 is read, until the counter 12 is read and the signal 6 is generated, the counters 11, 12 stops counting, then the read data of the counter 12 is 3FH and a 16-bit correct count value 3FFFH is read.</p> |
