发明名称 BACKGROUND DENSITY ADJUSTING CIRCUIT FOR OPTICAL READING SYSTEM
摘要 PURPOSE:To produce an excellent reproduction of an original that includes half tone by discriminating whether or not the image information is a background information, and by controlling the storage time of the information by the image sensor so that the peak value on the white-side of the information coincides with the prescribed reference value in case the information is discriminated as a background information. CONSTITUTION:Clock pulses CK1 and CK2 are obtained by a control signal generating circuit 11. The storage time adjusting part of the generating circuit 11 is composed of a variable divider 52 and a counter 51. The dividing ratio of the variable divider 52 is decided by the counter 51, and the divider 52 divides the CLK1 as referring to the dividing ratio, and forms the clock CK1. Therefore, the more the counter 51 counts up, the larger the dividing ratio is made, and the period of the output clock CK1 of the variable divider 52 becomes longer. Inversely, the counting down makes the dividing ratio smaller and the period of the same clock CK1 shorter. By adjusting the period of the clock signal in such a manner as above, the output voltage of an image sensor 10 is controlled to maintain the background density constant.
申请公布号 JPS61111072(A) 申请公布日期 1986.05.29
申请号 JP19840232942 申请日期 1984.11.05
申请人 FUJI XEROX CO LTD 发明人 YAMAMOTO TETSUMICHI
分类号 H04N1/407;H04N1/40 主分类号 H04N1/407
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