| 摘要 |
A bus apparatus (20) for interconnecting a plurality of nodes (25-28). The nodes may comprise processors (21, 22), input/output subsystems (23, 24), or the like. Each node maintain a unique priority number; the priority numbers are determined independently by each node. Separate updating of the priority numbers occurs for acknowledgement packets as compared to data transmissions. This provides for quick, efficient acknowledgement of transmissions and does not unfairly penalize a popular receiving node. Two different interface circuits are described, one particularly suitable for use with an input/output subsystem, and the other for a processor. |
