发明名称 COMPLEMENTARY MOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
摘要 PURPOSE:To make latch-up difficult to occur, and to reduce the electric capacitance of a diffused layer by a method wherein a buried layer of the same conductivity type as that of the substrate or the well and high impurity concentration is provided, and this buried layer is formed by covering the bottom of a transistor region. CONSTITUTION:A well of reverse conducvitity type to that of the semiconductor substrate of one conductivity type is provided in the substrate, and a transistor of reverse conductivity type channel to that of the substrate is formed in the substrate; then, a transistor of reverse conductivity type channel to that of the well is formed in the well. In such a complementary MOS semiconductor device, by connection to a diffused layer 33, a P type layer 34 is formed at the substrate interface under a field oxide film 28, and further a P<+> type layer 35 is formed in the substrate under the activating region. The P<+> type layer 35 is made larger than the P type substrate in concentration and formed by isolation in a depth below the bottom of the N type diffused layer of the N- channel transistor. In other words, with respect to the N-channel transistor, an excellent transistor without leakage current can be obtained by increasing the P type interface- concentration at the field part, and thus by increasing the threshold voltage of the field.
申请公布号 JPS6110268(A) 申请公布日期 1986.01.17
申请号 JP19840131464 申请日期 1984.06.26
申请人 NIPPON DENKI KK 发明人 ARAKI MINORU
分类号 H01L27/08;H01L21/76;H01L27/092 主分类号 H01L27/08
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