| 摘要 |
PURPOSE:To attain stable synchronizing separation even at sudden change in an input signal by inputting a synchronizing signal from the 1st synchronizing signal separating circuit to a PLL and activating the 2nd synchronizing signal separation circuit with a signal subjected to phase lock to separate the synchronizing signal. CONSTITUTION:A video signal at a terminal 12 is clamped at a peak clamp circuit 13, compared by a comparator 14 and a synchronizing signal 15 is outputted. The circuits 13, 14 constitute the 1st synchronizing signal separation circuit. The synchronizing signal 15 is inputted to a PLL circuit 16, a synchronizing signal 17 phase-locked to the synchronizing signal is outputted, inputted to a sample-and- hold circuit 20 to sample the synchronizing signal portion of the video signal 21. The value is amplified by an error amplifier 19 and the voltage is subjected to differential amplification. The video signal 21 clamped in a prescribed potential is subjected to synchronizing separation by a comparator 22. Even if the DC and AC component of the video signal are changed suddenly, a check signal 25 holds the phase error voltage of the PLL circuit 16, resulting that no synchronizing signal 17 is disturbed. |
