| 摘要 |
PURPOSE:To disperse the load of interruption process so as to reduce the overhead required for processing unnecessary interruption, by setting interrupting destinations to optional plural processors. CONSTITUTION:Writing and readout can be performed from an optional processor through a common bus 7 to an interrupted processor holding register 106 at one 61 of interrupted processor determining circuits. The common bus 7 is equipped with a data writing signal line 7a, data reading out signal line 7b, address bus 7c, data bus 7d, and address decoder 4. Moreover, an AND output, in which the value of the interrupted processor holding register 106 is included, is inputted in the interrupting port 21-24 of each processor. A signal line 107 is used when the register 106 is read out and another signal line 108 is used when writing operations are made in the register 106. The last signal line 91 is for inputting interruption from input-output devices 81-84.
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