| 摘要 |
PURPOSE:To shorten the read time by providing a data output driving signal transmitting circuit for every pair of data transfer nodes, which transfer read data as a potential change, to remove restrictions on the timing when a data output driving signal is set to the high level. CONSTITUTION:Pairs of data transfer nodes I/O1-I/O4 and -I/O1--I/O4 which transfer data read out from a memory as a potential change, nodes to which switch signals R1-R4 are inputted, nodes to which a data driving signal phiOUT is inputted, and a pair of data output driving signal transfer nodes N1 and N2 which can transfer a data output driving signal DOUT are provided. Plural data output driving signal transfer circuits which transfer the data output driving signal while following up the data potential change given to nodes N1 and N2 and switch signals R1-R4 are arranged in accordance with individual pairs of data transfer nodes I/O1, -I/O1-I/O4, and -I/O4. Thus, restrictions on the timing when the data output driving signal is set to the high level are removed to shorten the read time.
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