发明名称 ARITHMETIC UNIT FOR PROCESSING INPUT AND OUTPUT
摘要 <p>PURPOSE:To apply counters/timers, capture registers, and comparing registers to the control of various apparatuses, by giving degree of freedom to the numbers of the counters/timers, capture registers, and comparing registers. CONSTITUTION:An input-output task register section 205 is composed of a register group, each of which holds input-0output functional instruction data, and the functional instruction data are written in the registers 205 from microcomputer sections 200, 201, and 202 through a data bus 203. The functional instructions are successively read out and control an input-output calculating section 207 through a task decoder section 206 in accordance with the instructions. The decoder section 206 generates signals for controlling the calculating section 207 on the basis of the functional instruction data and the signal state of an input group 208. The calculating section 207 makes increment for counter/timers, transfers data to capture registers, compares the data of the counters/timers with those of comparing registers, and generates an output signal to an output group 209.</p>
申请公布号 JPS61110254(A) 申请公布日期 1986.05.28
申请号 JP19840230202 申请日期 1984.11.02
申请人 HITACHI LTD 发明人 MORINAGA SHIGEKI;WATABE MITSURU
分类号 G06F15/78;G04G15/00;G04G99/00 主分类号 G06F15/78
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