| 摘要 |
PURPOSE:To attain error control with high reliability by using an output of a C1 counter totalling an error estimated by an entire C1 decoding process and a C2 counter totalling an error estimated by the entire C2 decoding process so as to discriminate whether the erroneous state of a channel is to be corrected or not. CONSTITUTION:The information stored in a data RAM3 is subject to execution of C1 decoding by a control circuit 6. Then number of errors K1, K2...Kn1 dis criminated by decoding processes P1, P2...Pn1 are inputted to the C1 counter 54, where a number N1(c)is stored in discriminating circuit 56 as the total of errors at the decoding of the entire C1. Then the C2 decoding is executed by a command of the circuit 6. The number of errors discriminated by C2 decoding processes Q1, Q2...Qn2 are inputted to the C2 counter 55 as L1, L2...Ln2, and the number of N2(c) is stored in the discrimination circuit 56 as the total error at the entire C2 decoding. The circuits 55, 56 discriminate whether or not the erroneous state of a channel is to be corrected so as to reduce correction error and overlooking error.
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