发明名称 DELAY CHECKING SYSTEM
摘要 PURPOSE:To attain automatic and efficient delay check without manual operation by using signal changing data and making a computer select a signal path actually transmitting the signal change and required to be checked at its delay. CONSTITUTION:Logical data 1 describing a logical circuit and simulation data 2 describing a logical simulation method are inputted and the logical simulation 3 of the logical circuit is executed by a computer. A logical table 5 indicating the locations of respective signals in the logical circuit on the transmitting and receiving sides and signal changing data 6 indicating the changing status of respective signals are inputted and section specifying data 8 indicating the section of the signal path from the location of the signal changed in the logical simulation to the location of the final signal are found out by the computer. The data 8, 1 are inputted and the delay check 9 of only the signal path in the section specified by the sectional data in the logical circuit is executed by the computer.
申请公布号 JPS61108979(A) 申请公布日期 1986.05.27
申请号 JP19840229745 申请日期 1984.10.31
申请人 HITACHI LTD 发明人 ONIZUKA NOBUHIKO
分类号 G01R31/28;G06F11/273;G06F17/50 主分类号 G01R31/28
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