| 摘要 |
A multimicroprocessor system constructed of multimicroprocessor structures each including N-number of microprocessor units, a shared memory, an input/output unit and a register exchange circuit. The microprocessor units are uniform and include a microprocessor, a data memory, a parallel input-output interface, a sequential input/output circuit, a program memory and a bi-directional buffer. The buffer connects the internal data bus in the microprocessor unit to the shared instruction bus for the multimicroprocessor structure, and the enable inputs of the buffer are connected to the internal busses for circuit selection in the microprocessor unit by the microprocessor address lines. The address lines of the first microprocessor unit in the multimicroprocessor structure are connected also to a shared memory, input/output unit and both to the parallel data exchange register circuit and the "HALT" inputs of the microprocessors in the rest of the units through a logic circuit, which serves to switch off the microprocessor units. The multimicroprocessor structures are connected therebetween by first level data exchange register circuits, whose control inputs are connected to the address lines of the first microprocessor units in the respective first microprocessor structures. These first level register circuits are connected groupwise to a second level data exchange register circuit, whose control input is connected to the address lines of the microprocessor unit whose address lines are connected to the first of the first level data exchange register circuits.
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