发明名称 SUPERVISORY SYSTEM OF TIME DIVISION MULTIPLE ACCESS DEVICE
摘要 PURPOSE:To attain fault supervision with on-line and high reliability by inserting a supervisory pattern in a transmission data string and transmitting the result during time slots while no transmission burst is transmitted and extracting the supervisory pattern from the signal string so as to apply supervision. CONSTITUTION:A data signal of plural series is inputted to a synthesis circuit 2 via interface (IF) circuits 1a, 1b...1n. The logical processing is executed in the logical processing circuit 3 during time slots including a transmission data and a carrier signal in time slots other than the said time slots is shut off from a modulator 4. A supervisory pattern generating circuit 5 uses a data gate signal as a clock signal to generate the supervisory pattern, which is inserted to the time slot shut off by the modulator 4. A supervisory pattern detection circuit 6a supervises the synthesis circuit 2 by extracting the supervisory pattern inserted in the synthesis circuit 2 and detecting it. Similarly, a fault of device after the logical processing circuit 3 is detected respectively by a corresponding supervisory pattern detection circuit.
申请公布号 JPS61108234(A) 申请公布日期 1986.05.26
申请号 JP19840228878 申请日期 1984.11.01
申请人 NEC CORP 发明人 SAGA RYOKICHI
分类号 H04B7/15;H04B7/212;H04J3/14 主分类号 H04B7/15
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