| 摘要 |
PURPOSE:To dispose gate electrodes in a plane, and to ensure PEP by exposing the side wall of a capacitor formation prearranged region in an island region and leaving a gate-electrode formation prearranged region in a MOS transistor and a peripheral insulating film. CONSTITUTION:An oxide film 2 and a field groove 4 are formed to a p<-> type Si substrate 1, and a p type layer 5 for isolating elements is shaped to the bottom of the groove 4. A photo-resist 3 and the film 2 are removed, and an oxide film 6 is deposited and removed to flatly bury the film 6. The film 6 is etched to leave thickness required for isolating the elements in the groove 4, and the side wall of a MOS capacitor formation prearranged region is exposed. A first-layer polycrystalline silicon film is deposited, and a capacitor electrode 10 and gate electrodes 12 by a second-layer polycrystalline silicon film in a manner that the gate electrodes are not superposed to the electrode 10 are formed and used as word lines. The n<+> type layers 13, 14 as source-drain while employing the electrodes 10, 12 as makes and an element protective film 15 and an Al wiring 16 are shaped. |
