| 摘要 |
<p>PURPOSE:To attain multi-stage relaying by providing an oscillation means oscillated synchronously with a code string, a count means for oscillated output, a count means of an oscillated clock, a latch means of the code string and a lead-out means for latch output so as to eliminate the need for adjustment of a tuning circuit, decrease jitter and eliminate addition of timing deviation. CONSTITUTION:When a reception signal waveform is shown in figure A, an output of a gate signal detection circuit 1 is shown in figure B and a data start signal C is generated synchronously with its leading timing. Counters 5, 9 are both reset synchronously with the signal C to count oscillation clocks E, H or oscillators 4, 7. In this case, the clock E is oscillated synchronously with the leading timing of the data A. The data A is fetched to an SR6 synchronously with the clock E, and when the content of the counter 5 reaches a prescribed value, an output F is generated and the content of bit of the SR6 is latched in parallel with a latch circuit 8 in the timing of the output F. The latched content is fetched in parallel with an SR10 and this timing is made by an output G of a counter 9. The a regenerated data J is obtained by an oscillated clock H of the oscillator 7 without jitter from an SR9.</p> |
