| 摘要 |
PURPOSE:To eliminate the need for high speed circuit elements even when the transmission speed is increased by applying a check bit where bit length is expanded and level 1 conversion is applied to a check bit error detection circuit. CONSTITUTION:When a 4-bit serial signal S is inputted to a converting circuit SP, a parallel 4-bit signal is transmitted to an exclusive OR circuit EXOR from parallel output terminals A, B, C, D. In the bit arrangement shown in figure, numbers 1-11 indicate bit numbers of serial codes and the bit applied with hatch is the 11th check bit. When the output of the column A is the 10th bit, the output of the column B is the 11th bit, check bit, and both the signals are given to the EXOR1. When no code error exists, the input is the combination of 0, 1, level 1 appears in the output of the EXOR1 and if there is any error, the output is O. The code error of the check bit is supervised by detection circuits DET1-DET4. Further, a delay circuit DL brings signals of the columns A, D to the EXOR4 at the same time.
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