发明名称 CLOCK CONTROL CIRCUIT
摘要 PURPOSE:To attain low speed operation independently by synchronized/ asynchronized sample rate fS, Baud rate fB with each other by using a rate converting filter inputting a sample value series of the fS and outputting a sample value series interpolated with the fB as an interpolation filter so as to provide a time delay to the said filter. CONSTITUTION:A sample circuit 1 samples an input signal of a transmission period TB at a period of TS. A rate conversion filter circuit 2 outputs the 1st and 2nd interpolation values being the result of delay and interpolation of the input to the circuit 1 at each start pulse of a reference time generating circuit 5 according to the 1st and 2nd delay time amount outputted from an operating section 4. An error detection section 3 uses the said interpolation to output a surplus/deficient value DELTAT of the 1st delay amount. The operating section 4 inputs the output DELTAT and outputs the DELTAT and the 2nd delay time amount DELTAT+TB/2. The circuit 5 inputs the DELTAT and applies a start pulse to the filter 2 at a period of TB+DELTAT based on the period TS.
申请公布号 JPS61108236(A) 申请公布日期 1986.05.26
申请号 JP19840229508 申请日期 1984.10.31
申请人 NEC CORP 发明人 OOSAWA TOMOKI
分类号 H04L7/00;H04L7/02 主分类号 H04L7/00
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