发明名称 DATA TRANSFER CONTROL SYSTEM
摘要 PURPOSE:To reduce load to a CPU by allowing the I/O device which requests data transfer to perform setup operation to a register group in a data transfer controller. CONSTITUTION:When the I/O device 80-1 is allowed to use an external bus 20, it outputs an address, data, and write signal to an address bus 23, data bus 32, and read/write line 21 respectively. It specifies a derised register in the register group 52 of the data transfer controller 33 of the CPU 60, and completes the setup of the register group 52 separately from a processor 31. The data controller 33 makes the I/O equipment 80-1 and MM12 write status and read status respectively, and performs data transfer regardless of the CPU.
申请公布号 JPS61107457(A) 申请公布日期 1986.05.26
申请号 JP19840228516 申请日期 1984.10.30
申请人 TOSHIBA CORP 发明人 NIREGI TOORU
分类号 G06F13/28;G06F13/12 主分类号 G06F13/28
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