发明名称 INPUT LATCH CIRCUIT
摘要 PURPOSE:To pass an output of a latch circuit through a gate circuit only when both outputs of the latch circuit is in complementary relation by providing an exclusive OR circuit inputting the complementary output of the latch circuit and a gate circuit receiving the output of the exclusive OR circuit and the latch circuit. CONSTITUTION:A logical operation guarantee circuit 1 consists of the exclusive OR circuit comprising an NAND gate 11, an OR gate 12 and an AND gate 13, and of an AND gate. When a latch circuit L is activated normally, its Q, Q' outputs can be 1, 0 or 0, 1 being in complementary relation, then the exclusive OR circuit (EXOR) outputs logical 1 in this case only, and a gate 14 is set to obtain a correct output. That is, since the circuit 1 consists of the EXOR and the AND gate, even if the Q, Q' outputs are 1, 1 or 0, 0 because of a defective latch circuit L, the EXOR circuit outputs 0 and the AND gate 14 outputs 0 and clamped to detect the defect.
申请公布号 JPS61105922(A) 申请公布日期 1986.05.24
申请号 JP19840226676 申请日期 1984.10.30
申请人 FUJITSU LTD 发明人 WADA KENSAKU
分类号 H03K3/037 主分类号 H03K3/037
代理机构 代理人
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