| 摘要 |
PURPOSE:To make it possible to form test data easily at a high speed by combining a logic circuit part with a fault simulator by connecting it to a computer system as an emulator. CONSTITUTION:Emulator EML serves as one I/O channel and data sent from CPU via data bus 12 are stored in data register RG21 and selection RG22. Then, RG22 selects one of submodules SM231-SM23n and each SM has input RG24 and output RG26; and input data equivalent to the input terminal of LSI in RG21 are set in RG24 and its output signal is applied to normal LSI25 as EML to make RG remember variation corresponding to input variation. The contents of RG26 are transferred to RG21 and sent to CPU via bus 12. Performing fault simulation SML, CPU combines fault SML with EML to supplement input data and output data mutually, so that test data can easily be formed. |
