发明名称 MULTI-LINE TYPE MULTI-VALUE LOGIC CIRCUIT
摘要 PURPOSE:To execute the logical operation of, e.g., a logical simulator in terms of hardware while uncertain unstable state into account by constituting the titled circuit with a binary logical element and forming incoming and outgoing lines with plural pairs of signal lines through which a binary logical signal constituting multi-value logical information is transmitted respectively. CONSTITUTION:Logical information A, B are inputted to a logical operation circuit through two lines of A0, A1 and B0, B1 respectively and outputted from two lines -O1, -O0 as outgoing lines. The logical operation circuit consists of an AND circuit 1, an OR circuit 2, an AND circuit 3, an NOT circuit 4, and an NOR circuit 5. The signal relation of each part of the circuit is attained by the conventional binary logic. For example, only when all of the lines A0, A1, B0, B1 are logical 1, the output of the NAND circuit 1, that is, the -O1 goes to logical and in other case, the output goes to logical 1. Thus, the multi- value information is expressed as the sets of plural binary logic signals and the logical operation among multi-value logical information is realized by the circuit consisting of binary logical elements.
申请公布号 JPS61105119(A) 申请公布日期 1986.05.23
申请号 JP19840227319 申请日期 1984.10.29
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MATSUMOTO TAKASHI
分类号 G06F17/50;H03K19/20;(IPC1-7):H03K19/20 主分类号 G06F17/50
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