发明名称 DECODING OPERATION CIRCUIT OF ERROR CORRECTION CODE
摘要 PURPOSE:To realize circuit integration with a small area by providing a memory section comprising respectively memory circuits used for the calculation of each syndrome and a common multiplication section and addition section to execute plural syndrome operations while being shifted timewise. CONSTITUTION:Syndromes S0, S1, S2 and S3 are calculated timewise in order. At first contents of memory sections 11, 21, 31, 41 are reset. Then a control signal to turn on each switch of a switch section 60 is inputted and the 1st reception data Vn-1 is inputted to an addition section 52 from a reception data line 4. A data VIC of the memory section 11 is inputted to the addition section 52 via a multiplication section 70 similarly at the same time, added to the reception data Vn-1, and the sum is inputted to the memory section 11. Further, four times in total of similar operation as above are repeated to control signals T0-T3 and the 3rd n-th reception data Vn-3-V0 to calculate syndromes S0, S1, S2, S3 and input them to the memory sections 11-14 respectively.
申请公布号 JPS61105123(A) 申请公布日期 1986.05.23
申请号 JP19840226119 申请日期 1984.10.27
申请人 MITSUBISHI ELECTRIC CORP 发明人 MASUDA NORITAKA;HONGO KATSUNOBU
分类号 H03M13/00;G06F11/10 主分类号 H03M13/00
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