| 摘要 |
PURPOSE:To obtain a dynamic RAM with which an input/output function is improved by converting successively the read signals sent from each memory array into serial signals from the indicated memory arrays according to combinations of prescribed address signals. CONSTITUTION:Either one of control signals phia and phib is set at a high level for each memory mat by the combination of 2-bit address signals AX0 and AX1 which designate memory mats MA1-MA4. Then either one of word lines (w) is selected at each mat by the rise of a word line selection timing signal phix. When the mat MA1, for example, is designated, a transfer gate MOSFETQ 10 is first turned on. Then Q11-Q13 are turned on and the read signals are transmitted successively and serially through an external terminal Dout from the mat MA1. Then the 4-bit signals are transmitted serially in the same way when a new Y address is designated.
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