| 摘要 |
PURPOSE:To keep falsely a geometrical linking condition and to minimize the reduction of the whole peformance by changing over a communication bus fat and acting for the processing with a load share by an adjoining processor even when the processor partially breaks down. CONSTITUTION:When the processor (a) breaks down, a bus changeover signal (g) is outputted from a placed trouble detecting circuit (f). Next, due to the signal (g) set to a low level by an inverting terminal of a transmitter (m), a data transceiver (e) becomes invalid, a usual bus (d) is separated, and while the signal (g) is a high level, a data transceiver (j) becomes valid. Thus, processors (b) and (c) are linked by a trouble relaying bus (k). Next, the signal (g) is inputted to the processor (b) and the processor (b) executed the data processing in place of the processor (a). Thus, even when the processor (a) breaks down, by changing over the bus, the adjoining processor acts for the troubled processor, therefore, the whole performance reduction can be minimized.
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