| 摘要 |
PURPOSE:To decide surely input disconnection by applying the result of comparison between a reception equalizing output signal with threshold value and a clock of a different phase near an identifying point of the reception equalizing signal to plural FFs and obtaining an exclusive OR of outputs of the FFs. CONSTITUTION:A reception signal is subject to amplification 1, equalization 2 and fed to an identification circuit, a clock regenerating circuit 4 and a comparator circuit 5. The circuit 4 generates a clock selecting an identification timing of the identification circuit 3 and also generates plural clocks near the former clock and they are fed to a clock terminal C for the FF6-1-6-n. The comparator circuit 5 uses transistors (TRs) Q1, Q2, compares a threshold voltage Vdd.R6/(R6+R7) and the input signal, and outputs logical H when the input signal is higher than the threshold value and gives it to a data terminal D of the FF6-1-6-n. Outputs of the FFs are fed to an exclusive OR circuit 7, and when all inputs are not arranged, logical 1 is outputted, the number of logical 1s is counted (8) and when the number reaches a prescribed number of times within a prescribed time, an alarm is outputted (9). Thus, input disconnection is decided accurately.
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