| 摘要 |
PURPOSE:To simplify a circuit construction and to reduce an error of a code by feeding a parallel N bit output of a cyclic calculating means as a data length adjusting code to a parallel column converting means, feeding it as a frame inspecting code to a parallel serial converting converting means after the feeding of this data length adjusting code is completed, and feeding a data code, the data length adjusting code and the frame inspecting code, successively. CONSTITUTION:After an N bit signal outputted from a latch circuit 42 is converted into a serial bit by a serializer 21, it is fed to a CRC calculating circuit 30 in order to count a frame inspecting code. When feed of a patting data PAD is completed, latch signals LS1-LS4 are successively generated with respect to respective latch circuits 41-44 from a control circuit. Thereby, the latch circuits 41-44 at that time latch a parallel signal outputted from the CRC calculating circuit 30, that is, the frame inspecting signal by N bit successively and output to a data bus DBUS. As a result, from a serializer 22, the N bit signal outputted successively from the respective latch circuits 41-44 is fed as the frame inspecting signal.
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