| 摘要 |
PURPOSE:To execute highly speedy and efficient data processing by writing temporarily a receiving data in a receiving data memory circuit referring to an identifying code, reading the receiving data from the memory circuit after a (n) number offrames and converting divided receiving data to the receiving data row at a the circuit which reads later on. CONSTITUTION:An input receiving data signal 10 devided over a (n) number of frames is arranged from an address pointed by the identifying code 8 to an area offset up to a (n) number. On the other hand, input output receiving data from the first memory circuit are read by the first memory circuit reading address signal 14 between next multi-frames. A circuit plan 13 for receiving data row corresponds to an identifying code part of the first memory circuit writing address signal 11 and defines a sequence to read receiving data of respective lines from the memory circuit 3. Consequently, when the arrangement of the burst-shaped data of respective lines is changed, the reading sequence of the circuit plan 13 for thereceiving row is kept constant and will not be accessed to an unnecessary address of the memory circuit 3. |
