| 发明名称 |
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| 摘要 |
In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module. |
| 申请公布号 |
JPS6120017(B2) |
申请公布日期 |
1986.05.20 |
| 申请号 |
JP19820057424 |
申请日期 |
1982.04.08 |
| 申请人 |
TANDEMU KONPYUUTAAZU INC |
发明人 |
JEEMUSU AREN KATSUTSUMAN;JOERU FUORUSOMU BAATORETSUTO;RICHAADO MATSUKU KURODO BIKUSURAA;UIRIAMU HENRII DEIBITSUDOO;JON AREKISANDAA DESUHOTAKISU;PIITAA JON GURAJIANO;MITSUCHERU DENISU GURIIN;DEBITSUDO |
| 分类号 |
G06F11/18;G06F1/26;G06F5/06;G06F7/78;G06F9/46;G06F9/52;G06F11/00;G06F11/10;G06F11/16;G06F11/20;G06F12/08;G06F12/10;G06F12/12;G06F12/14;G06F13/00;G06F13/12;G06F13/20;G06F13/28;G06F13/366;G06F13/38;G06F15/16;G06F15/167;G06F15/173 |
主分类号 |
G06F11/18 |
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