| 摘要 |
PURPOSE:To reduce the amount of hardware and to improve the arithmetic speed by adopting the architecture of a processor limiting a part handling data generation in an exponential part fixed length expression in the processor to attain a semiconductor integrated circuit processor possible for data arithmetic in the exponential part variable length expression. CONSTITUTION:In a data storage section 110, exponential part variable length floating decimal point data is used for data in an instruction control section 170 on a data bus and exponential part fixed length floating decimal point data is used for data in an arithmetic section 140 and an arithmetic result storage section 150. Further, a data converting section 130 has a function converting the exponential part variable length floating decimal point data into the exponential part fixed length floating decimal point data and a data converting section 160 has a function converting reversely the data as that of the data converting section 130. The hardware is reduced by adopting the data form of exponential part variable length expression to the storage section 110 and the data bus. Further, the adoption of the data form of the exponential part variable length expression for the storage section 150 allows the improvement of the arithmetic speed. |
