| 摘要 |
PURPOSE:To optionally set the data transmission rate while prefetching the write data and to prevent an overrun by setting the initial value of a shift register. CONSTITUTION:A central controller 1 and an external memory device 3 are connected by a controller 2 to constitute an electronic computer system. A channel interface control part 5, a buffer control part 6, and a device interface control part 7 of this controller 2 are controlled by a microprocessor 4. A channel interface part 8 connected to the central controller 1 is connected to the control part 5. The output signal of the processor 4 is supplied to the signal lines 11-1-11-7 of a shift register 20 of the control part 5, and load signal is supplied to a signal line 11-1. The output of the register 20 and that of a timing pulse generator 27 are logicalized by ANDs 22-24 and an OR 25. The data transmission indication signal 12 from the output of said circuits is taken for the initial value of a register 20, to optionally set the data transmission rate amid the write data prefetching. |
