发明名称 TIMING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To obtain a circuit whose characteristic is immune to fluctuation against a temperature change or a power supply voltage change suitable for circuit integration by activating a time constant circuit deciding the period of an output binary signal (timing signal) with the logical operation output between an inputted binary signal and an output binary signal. CONSTITUTION:A level of an output terminal 6 of a comparator 13 keeps a high level until a level at a terminal 5 exceeds a level of a +input 7 of the comparator 13 and since one input to an NOR circuit 12 is at a high level, an output terminal 9 of the NOR circuit 12 keeps a low level even if a transistor (TR) Q1 is turned on/off during this time and TRs Q4, Q11 keep the off-state, then the level of the output terminal 6 keeps the low level. When the level at the terminal 5 exceeds the level of the input 7, the output 6 of the comparator 13 is inverted to a low level and when the level of a line 8 is decreased to the low level, since the TRs Q4, Q11 is turned on, a capacitor C1 is brought again into the initial state.
申请公布号 JPS61101114(A) 申请公布日期 1986.05.20
申请号 JP19840222203 申请日期 1984.10.24
申请人 CANON INC 发明人 ICHINOSE TOSHIHIKO
分类号 H04N5/06;H03K3/0232;H03K3/282;H03K5/04 主分类号 H04N5/06
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